TY  - JOUR
  - O'Mahony, C.,Hill, M.,Olszewski, Z.,Blake, A.
  - 2009
  - June
  - Microelectronic Engineering
  - Wafer-level thin-film encapsulation for MEMS
  - Validated
  - ()
  - 86
  - 4-64-6
  - 1311
  - 13131311
  - The diversity and complexity of many microelectromechanical systems (MEMS), combined with the mechanical nature of the devices involved, means that the handling, dicing and packaging of these structures can pose many problems. So-called 'zero-level' packaging options are now often used to protect the devices at the wafer scale before the wafer is diced and sent for conventional packaging. This paper describes a novel process flow for the fabrication of integrated MEMS thin-film packages within a low-temperature, CMOS-compatible process. A double sacrificial layer is used, which encapsulates the device of interest within a shell of silicon oxide. The sacrificial layer is then removed through lateral etch channels and the shell is sealed. The technique requires minimal extra wafer space, allows the use of low-temperature materials within the process flow, and the novel channel design means that the shell may be easily sealed. Preliminary visual and electromechanical tests using simple fixed-fixed beam test structures indicate that the package is sealed, the device is undamaged and that encapsulation has little or no effect on device performance. (C) 2008 Elsevier B.V. All rights reserved.The diversity and complexity of many microelectromechanical systems (MEMS), combined with the mechanical nature of the devices involved, means that the handling, dicing and packaging of these structures can pose many problems. So-called 'zero-level' packaging options are now often used to protect the devices at the wafer scale before the wafer is diced and sent for conventional packaging. This paper describes a novel process flow for the fabrication of integrated MEMS thin-film packages within a low-temperature, CMOS-compatible process. A double sacrificial layer is used, which encapsulates the device of interest within a shell of silicon oxide. The sacrificial layer is then removed through lateral etch channels and the shell is sealed. The technique requires minimal extra wafer space, allows the use of low-temperature materials within the process flow, and the novel channel design means that the shell may be easily sealed. Preliminary visual and electromechanical tests using simple fixed-fixed beam test structures indicate that the package is sealed, the device is undamaged and that encapsulation has little or no effect on device performance. (C) 2008 Elsevier B.V. All rights reserved.
  - 0167-93170167-9317
  - ://000267273300225://000267273300225
DA  - 2009/06
ER  - 

@article{V179169559,
   = {O'Mahony,  C. and Hill,  M. and Olszewski,  Z. and Blake,  A. },
   = {2009},
   = {June},
   = {Microelectronic Engineering},
   = {Wafer-level thin-film encapsulation for MEMS},
   = {Validated},
   = {()},
   = {86},
   = {4-64-6},
  pages = {1311--13131311},
   = {{The diversity and complexity of many microelectromechanical systems (MEMS), combined with the mechanical nature of the devices involved, means that the handling, dicing and packaging of these structures can pose many problems. So-called 'zero-level' packaging options are now often used to protect the devices at the wafer scale before the wafer is diced and sent for conventional packaging. This paper describes a novel process flow for the fabrication of integrated MEMS thin-film packages within a low-temperature, CMOS-compatible process. A double sacrificial layer is used, which encapsulates the device of interest within a shell of silicon oxide. The sacrificial layer is then removed through lateral etch channels and the shell is sealed. The technique requires minimal extra wafer space, allows the use of low-temperature materials within the process flow, and the novel channel design means that the shell may be easily sealed. Preliminary visual and electromechanical tests using simple fixed-fixed beam test structures indicate that the package is sealed, the device is undamaged and that encapsulation has little or no effect on device performance. (C) 2008 Elsevier B.V. All rights reserved.The diversity and complexity of many microelectromechanical systems (MEMS), combined with the mechanical nature of the devices involved, means that the handling, dicing and packaging of these structures can pose many problems. So-called 'zero-level' packaging options are now often used to protect the devices at the wafer scale before the wafer is diced and sent for conventional packaging. This paper describes a novel process flow for the fabrication of integrated MEMS thin-film packages within a low-temperature, CMOS-compatible process. A double sacrificial layer is used, which encapsulates the device of interest within a shell of silicon oxide. The sacrificial layer is then removed through lateral etch channels and the shell is sealed. The technique requires minimal extra wafer space, allows the use of low-temperature materials within the process flow, and the novel channel design means that the shell may be easily sealed. Preliminary visual and electromechanical tests using simple fixed-fixed beam test structures indicate that the package is sealed, the device is undamaged and that encapsulation has little or no effect on device performance. (C) 2008 Elsevier B.V. All rights reserved.}},
  issn = {0167-93170167-9317},
   = {://000267273300225://000267273300225},
  source = {IRIS}
}