FPGA implementations of LDPC over GF(2^m) decoders

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TY  - CONF
  - Christian Spagnol, William Marnane, Emanuel Popovici
  - IEEE 2007 Workshop on Signal Processing Systems (SiPS)
  - FPGA implementations of LDPC over GF(2^m) decoders
  - 2007
  - October
  - Published
  - 1
  - Scopus: 27 ()
  - Block codes, Decoding, Galois Fields, FPGA
  - 273
  - 278
  - Shanghai, China
  - 17-OCT-07
  - 19-OCT-07
  - Low Density Parity Check (LDPC) codes over GF(2m) are an extension of binary LDPC codes that have not been studied extensively. Performances of GF(2m) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there iS a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper presents a FPGA serial implementation of two decoding algorithms for LDPC over GF(2m). The results prove that the implementation of LDPC over GF(2m) decoding is feasible and the extra complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes.
  - 10.1109/SIPS.2007.4387557
DA  - 2007/10
ER  - 
@inproceedings{V1194794,
   = {Christian Spagnol,  William Marnane and  Emanuel Popovici },
   = {IEEE 2007 Workshop on Signal Processing Systems (SiPS)},
   = {{FPGA implementations of LDPC over GF(2^m) decoders}},
   = {2007},
   = {October},
   = {Published},
   = {1},
   = {Scopus: 27 ()},
   = {Block codes, Decoding, Galois Fields, FPGA},
  pages = {273--278},
   = {Shanghai, China},
  month = {Oct},
   = {19-OCT-07},
   = {{Low Density Parity Check (LDPC) codes over GF(2m) are an extension of binary LDPC codes that have not been studied extensively. Performances of GF(2m) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there iS a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper presents a FPGA serial implementation of two decoding algorithms for LDPC over GF(2m). The results prove that the implementation of LDPC over GF(2m) decoding is feasible and the extra complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes.}},
   = {10.1109/SIPS.2007.4387557},
  source = {IRIS}
}
AUTHORSChristian Spagnol, William Marnane, Emanuel Popovici
TITLEIEEE 2007 Workshop on Signal Processing Systems (SiPS)
PUBLICATION_NAMEFPGA implementations of LDPC over GF(2^m) decoders
YEAR2007
MONTHOctober
STATUSPublished
PEER_REVIEW1
TIMES_CITEDScopus: 27 ()
SEARCH_KEYWORDBlock codes, Decoding, Galois Fields, FPGA
EDITORS
START_PAGE273
END_PAGE278
LOCATIONShanghai, China
START_DATE17-OCT-07
END_DATE19-OCT-07
ABSTRACTLow Density Parity Check (LDPC) codes over GF(2m) are an extension of binary LDPC codes that have not been studied extensively. Performances of GF(2m) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there iS a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper presents a FPGA serial implementation of two decoding algorithms for LDPC over GF(2m). The results prove that the implementation of LDPC over GF(2m) decoding is feasible and the extra complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes.
FUNDED_BY
URL
DOI_LINK10.1109/SIPS.2007.4387557
FUNDING_BODY
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