IRIS publication 160960305
Algorithms and architectures for use in FPGA implementations of identity based encryption schemes
RIS format for Endnote and similar
TY - - Other - Kerins, T,Popovici, E,Marnane, W - 2004 - March - Algorithms and architectures for use in FPGA implementations of identity based encryption schemes - Validated - 1 - () - In this paper algorithms and architectures for new GF(3(m)) multiplier and inverter components are presented. It is described how they can be utilized as part of a hardware implementation of an Identity Based Encryption (IBE) scheme. The main computation, the Tate pairing in such a scheme in outlined and it is illustrated how it can be implemented on reconfigurable hardware using these components. - 74 - 83 DA - 2004/03 ER -
BIBTeX format for JabRef and similar
@misc{V160960305, = {Other}, = {Kerins, T and Popovici, E and Marnane, W }, = {2004}, = {March}, = {Algorithms and architectures for use in FPGA implementations of identity based encryption schemes}, = {Validated}, = {1}, = {()}, = {{In this paper algorithms and architectures for new GF(3(m)) multiplier and inverter components are presented. It is described how they can be utilized as part of a hardware implementation of an Identity Based Encryption (IBE) scheme. The main computation, the Tate pairing in such a scheme in outlined and it is illustrated how it can be implemented on reconfigurable hardware using these components.}}, pages = {74--83}, source = {IRIS} }
Data as stored in IRIS
OTHER_PUB_TYPE | Other | ||
AUTHORS | Kerins, T,Popovici, E,Marnane, W | ||
YEAR | 2004 | ||
MONTH | March | ||
TITLE | Algorithms and architectures for use in FPGA implementations of identity based encryption schemes | ||
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STATUS | Validated | ||
PEER_REVIEW | 1 | ||
TIMES_CITED | () | ||
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ABSTRACT | In this paper algorithms and architectures for new GF(3(m)) multiplier and inverter components are presented. It is described how they can be utilized as part of a hardware implementation of an Identity Based Encryption (IBE) scheme. The main computation, the Tate pairing in such a scheme in outlined and it is illustrated how it can be implemented on reconfigurable hardware using these components. | ||
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START_PAGE | 74 | ||
END_PAGE | 83 | ||
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