Design of a low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit using a Bidirectional Adder

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TY  - CONF
  - J.Chen, D. Vasudevan, E. Popovici and M. Schellekens
  - The 14th Euro-Micro International Conference on Digital System Design, Euro-Micro DSD
  - Design of a low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit using a Bidirectional Adder
  - 2011
  - September
  - Published
  - 1
  - ()
DA  - 2011/09
ER  - 
@inproceedings{V248927459,
   = {J.Chen, D. Vasudevan, E. Popovici and M. Schellekens},
   = {The 14th Euro-Micro International Conference on Digital System Design, Euro-Micro DSD},
   = {{Design of a low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit using a Bidirectional Adder}},
   = {2011},
   = {September},
   = {Published},
   = {1},
   = {()},
  source = {IRIS}
}
AUTHORSJ.Chen, D. Vasudevan, E. Popovici and M. Schellekens
TITLEThe 14th Euro-Micro International Conference on Digital System Design, Euro-Micro DSD
PUBLICATION_NAMEDesign of a low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit using a Bidirectional Adder
YEAR2011
MONTHSeptember
STATUSPublished
PEER_REVIEW1
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