Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder

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TY  - CONF
  - Chen, Jiaoyan and Vasudevan, Dilip and Popovici, Emanuel and Schellekens, Michel
  - Digital System Design (DSD), 2011 14th Euromicro Conference on
  - Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder
  - 2011
  - January
  - Validated
  - ()
  - 301
  - 308
DA  - 2011/01
ER  - 
@inproceedings{V277991437,
   = {Chen, Jiaoyan and Vasudevan, Dilip and Popovici, Emanuel and Schellekens, Michel},
   = {Digital System Design (DSD), 2011 14th Euromicro Conference on},
   = {{Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder}},
   = {2011},
   = {January},
   = {Validated},
   = {()},
  pages = {301--308},
  source = {IRIS}
}
AUTHORSChen, Jiaoyan and Vasudevan, Dilip and Popovici, Emanuel and Schellekens, Michel
TITLEDigital System Design (DSD), 2011 14th Euromicro Conference on
PUBLICATION_NAMEDesign of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder
YEAR2011
MONTHJanuary
STATUSValidated
PEER_REVIEW
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START_PAGE301
END_PAGE308
LOCATION
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END_DATE
ABSTRACT
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