An Efficient VLSI Architecture for Systematic Hermitian Encoder and Syndrome Generator

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TY  - JOUR
  - Agarwal, Rachit and K\"otter, Ralf and Popovici, Emanuel
  - 2008
  - January
  - IEEE TRANSACTIONS ON COMPUTERS
  - An Efficient VLSI Architecture for Systematic Hermitian Encoder and Syndrome Generator
  - Validated
  - 1
DA  - 2008/01
ER  - 
@article{V277991447,
   = {Agarwal, Rachit and K\"otter, Ralf and Popovici, Emanuel},
   = {2008},
   = {January},
   = {IEEE TRANSACTIONS ON COMPUTERS},
   = {An Efficient VLSI Architecture for Systematic Hermitian Encoder and Syndrome Generator},
   = {Validated},
  pages = {1},
  source = {IRIS}
}
AUTHORSAgarwal, Rachit and K\"otter, Ralf and Popovici, Emanuel
YEAR2008
MONTHJanuary
JOURNALIEEE TRANSACTIONS ON COMPUTERS
TITLEAn Efficient VLSI Architecture for Systematic Hermitian Encoder and Syndrome Generator
STATUSValidated
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