Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits

Typeset version

 

TY  - CONF
  - Amaricai, Alexandru and Nimara, Sergiu and Boncalo, Oana and Chen, Jiaoyan and Popovici, Emanuel
  - Digital System Design (DSD), 2014 17th Euromicro Conference on
  - Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits
  - 2014
  - January
  - Validated
  - 0
  - ()
  - 473
  - 479
DA  - 2014/01
ER  - 
@inproceedings{V277991534,
   = {Amaricai, Alexandru and Nimara, Sergiu and Boncalo, Oana and Chen, Jiaoyan and Popovici, Emanuel},
   = {Digital System Design (DSD), 2014 17th Euromicro Conference on},
   = {{Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits}},
   = {2014},
   = {January},
   = {Validated},
   = {0},
   = {()},
  pages = {473--479},
  source = {IRIS}
}
AUTHORSAmaricai, Alexandru and Nimara, Sergiu and Boncalo, Oana and Chen, Jiaoyan and Popovici, Emanuel
TITLEDigital System Design (DSD), 2014 17th Euromicro Conference on
PUBLICATION_NAMEProbabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits
YEAR2014
MONTHJanuary
STATUSValidated
PEER_REVIEW0
TIMES_CITED()
SEARCH_KEYWORD
EDITORS
START_PAGE473
END_PAGE479
LOCATION
START_DATE
END_DATE
ABSTRACT
FUNDED_BY
URL
DOI_LINK
FUNDING_BODY
GRANT_DETAILS