IRIS publication 160960595
Improving the accuracy and efficiency of junction capacitance characterization: Strategies for probing configuration and data set size
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TY - JOUR - MacSweeney, D,McCarthy, KG,Floyd, L,Duane, R,Hurley, P,Power, JA,Kelly, SC,Mathewson, A - 2003 - March - IEEE Transactions on Semiconductor Manufacturing - Improving the accuracy and efficiency of junction capacitance characterization: Strategies for probing configuration and data set size - Validated - () - bipolar and BiCNIOS processes bipolar transistors capacitance measurement parameter estimation DESIGN - 16 - 207 - 214 - In this paper, the on-wafer measurement of junction depletion capacitance is examined This work provides-an in-depth discussion of possible probing configurations which can be used. It outlines a method to consistently measure. the junction capacitances accurately. The results from this method compare favorably with those extracted using S-parameter measurements. Additionally, methods are formulated to reduce the number of data points required for parameter extraction while at the same time maintaining a high model accuracy. - DOI 10.1109/TSM.2003.811577 DA - 2003/03 ER -
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@article{V160960595, = {MacSweeney, D and McCarthy, KG and Floyd, L and Duane, R and Hurley, P and Power, JA and Kelly, SC and Mathewson, A }, = {2003}, = {March}, = {IEEE Transactions on Semiconductor Manufacturing}, = {Improving the accuracy and efficiency of junction capacitance characterization: Strategies for probing configuration and data set size}, = {Validated}, = {()}, = {bipolar and BiCNIOS processes bipolar transistors capacitance measurement parameter estimation DESIGN}, = {16}, pages = {207--214}, = {{In this paper, the on-wafer measurement of junction depletion capacitance is examined This work provides-an in-depth discussion of possible probing configurations which can be used. It outlines a method to consistently measure. the junction capacitances accurately. The results from this method compare favorably with those extracted using S-parameter measurements. Additionally, methods are formulated to reduce the number of data points required for parameter extraction while at the same time maintaining a high model accuracy.}}, = {DOI 10.1109/TSM.2003.811577}, source = {IRIS} }
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AUTHORS | MacSweeney, D,McCarthy, KG,Floyd, L,Duane, R,Hurley, P,Power, JA,Kelly, SC,Mathewson, A | ||
YEAR | 2003 | ||
MONTH | March | ||
JOURNAL_CODE | IEEE Transactions on Semiconductor Manufacturing | ||
TITLE | Improving the accuracy and efficiency of junction capacitance characterization: Strategies for probing configuration and data set size | ||
STATUS | Validated | ||
TIMES_CITED | () | ||
SEARCH_KEYWORD | bipolar and BiCNIOS processes bipolar transistors capacitance measurement parameter estimation DESIGN | ||
VOLUME | 16 | ||
ISSUE | |||
START_PAGE | 207 | ||
END_PAGE | 214 | ||
ABSTRACT | In this paper, the on-wafer measurement of junction depletion capacitance is examined This work provides-an in-depth discussion of possible probing configurations which can be used. It outlines a method to consistently measure. the junction capacitances accurately. The results from this method compare favorably with those extracted using S-parameter measurements. Additionally, methods are formulated to reduce the number of data points required for parameter extraction while at the same time maintaining a high model accuracy. | ||
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DOI_LINK | DOI 10.1109/TSM.2003.811577 | ||
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