TY  - 
  - Other
  - Cronin, D, Morrison, AP, McCarthy, KG
  - 2006
  - June
  - Hybrid Integration of A Cmos Active Quench and Reset Circuit For A Geiger-Mode Avalanche Photodiode - Art. No. 61240r
  - Validated
  - 1
  - ()
  - An active quench and reset circuit (AQRC) is an essential control circuit for ensuring high-speed photon counting with geiger-mode avalanche photodiodes (GMAPs). Its purpose is to turn off the detector when an avalanche has been detected, register a photon count and then reset the device to its quiescent bias voltage after a preset interval, to enable further avalanche events to be counted. This paper presents an AQRC-IC, developed using Europractice's ASIC Service. The purpose of the design was to develop a high-speed CMOS AQRC for hybrid integration with in-house GMAPs. The designed ASIC, developed using AMS' 3.3 V 0.35 mu m CMOS process models, includes a ballast resistor for the external GMAP, a comparator sensing-stage, an active quench and an active reset stage. The hold-off time is determined using external silicon delay lines and an FPGA. The ASIC is implemented on a ceramic DIP as is the GMAP, and the AQRC prototype achieves a saturated count-rate of 5 Mcounts/s, an active quench of 45 ns, an active reset of 30 ns and possible increments of the hold-off time between 50 ns and 500 ns..
  - 1240
  - 1240
  - DOI 10.1117/12.644108
DA  - 2006/06
ER  - 

@misc{V728591,
   = {Other},
   = {Cronin,  D and  Morrison,  AP and  McCarthy,  KG },
   = {2006},
   = {June},
   = {Hybrid Integration of A Cmos Active Quench and Reset Circuit For A Geiger-Mode Avalanche Photodiode - Art. No. 61240r},
   = {Validated},
   = {1},
   = {()},
   = {{An active quench and reset circuit (AQRC) is an essential control circuit for ensuring high-speed photon counting with geiger-mode avalanche photodiodes (GMAPs). Its purpose is to turn off the detector when an avalanche has been detected, register a photon count and then reset the device to its quiescent bias voltage after a preset interval, to enable further avalanche events to be counted. This paper presents an AQRC-IC, developed using Europractice's ASIC Service. The purpose of the design was to develop a high-speed CMOS AQRC for hybrid integration with in-house GMAPs. The designed ASIC, developed using AMS' 3.3 V 0.35 mu m CMOS process models, includes a ballast resistor for the external GMAP, a comparator sensing-stage, an active quench and an active reset stage. The hold-off time is determined using external silicon delay lines and an FPGA. The ASIC is implemented on a ceramic DIP as is the GMAP, and the AQRC prototype achieves a saturated count-rate of 5 Mcounts/s, an active quench of 45 ns, an active reset of 30 ns and possible increments of the hold-off time between 50 ns and 500 ns..}},
  pages = {1240--1240},
   = {DOI 10.1117/12.644108},
  source = {IRIS}
}